Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
Conventionally, a PLD is provided at least one external clock signal to generate at least one internal clock signal to operate internal components, including digital circuits. An external oscillator and clock networks are conventionally used to provide external clock signals.
Performance of a PLD may be adversely affected by a timing clock input signal having instability issues such as jitter and skew. Variations in at least one of clock signal frequency and phase may lead to incorrect operation of a PLD.
Others have attempted to resolve clock signal stability issues by relying on phase locked loops (PLLs). However, PLL implementations conventionally rely on a reference oscillator, such as voltage controlled crystal oscillator (VCXO) that is sensitive to vibration and thermal drift. Such a VCXO can add significant cost.
Others have compared an output clock signal of a PLD to an external clock signal input to such a PLD. Unfortunately, signal noise associated with input/output (I/O) signals used in operation of a PLD may introduce noise during a measurement, which noise reduces accuracy of a comparison between an output clock signal and an input clock signal. To address this inaccuracy, expensive external measurement systems, such as oscilloscopes, specialized clock signal measurement systems, and the like are used.
Accordingly, it would be desirable and useful to provide a reliable and cost effective measurement means to determine clock signal performance. Moreover, it would be desirable and useful to provide for on-chip measurement of at least one aspect of clock signal performance to avoid having to use expensive external equipment to measure such performance.